1. Field of the Invention
This invention relates in general to electronic circuits and in particular to DC offset correction circuits.
2. Description of the Related Art
Product designers today are being challenged to continuously create smaller and yet more sophisticated and more powerful electronic communication devices. To achieve this smaller size and more powerful performance, direct conversion and very low intermediate frequency (VLIF) receiver circuits are frequently used radio architectures.
The forward gain path for a direct conversion or very low intermediate frequency receiver has substantial power and/or voltage gain. The amplifiers in the forward gain path have some static or direct current (DC) offset from their respective differential input stages, current mirrors, etc. that are amplified at the their output stage. This DC offset manifests itself as a progressively degraded signal dynamic range in the forward gain path from the radio frequency (RF) fronted to the demodulator backend. Thus a DC offset correction scheme is required to ensure that the optimum signal dynamic range of each of the blocks within the forward gain path is maintained. Failure to do so will result in one or more of the forward gain blocks to clip the incoming signal thereby generating severe amounts of in-band harmonic distortion.
The DC offset correction loop is viewed as an essential requirement in direct-conversion receivers. Traditionally, a continuous time (C.T.) analog DC offset correction loop has been employed. A conventional receiver 10 utilized in radio communication systems and employing a C.T. analog DC offset correction loop is illustrated in FIG. 1. The conventional receiver 10 includes an antenna 12, a preselector 13, a radio frequency (RF) amplifier 14, a radio frequency (RF) mixer 16, an intermediate frequency (IF) filter 18, an intermediate frequency (IF) amplifier 20, an intermediate frequency (IF) mixer 22, a low pass filter 24, and an analog DC offset circuit 26.
The conventional receiver 10 receives a radio frequency (RF) signal 28 sent from a radio communication system 30 that is in a digital format or an analog format using the antenna 12. The preselector 13 filters the received RF signal 28 and passes it to the RF amplifier 14. The RF amplifier 14 then amplifies the radio frequency (RF) signal 28 and passes an amplified RF signal 32. The RF mixer 16 is coupled to a local oscillator 36 so as to produce an intermediate frequency (IF) signal 34 which can be, for example, a very low IF signal or a Zero-IF signal. The frequency of the IF signal 34 is the separation in frequency between the radio frequency signal and the local oscillator signals. The filter 18 generates a filtered IF signal 38 as well as removes spurious components of the IF signal 34 to improve the selectivity of the receiver and reduces the adjacent channel interference.
The intermediate frequency (IF) amplifier 20, which is coupled to the filter 18, is used to amplify the filtered IF signal 38 thereby generating an amplified IF signal 40. The IF mixer 22 then mixes the amplified IF signal 40 down to base band using a reference frequency 42 to produce a baseband signal 44. The IF filter 24 filters the baseband signal 44 to generate an output signal 46. The output signal 46 is passed to the backend 48 for further processing, such as demodulation. The analog DC offset circuit 26 is coupled between the backend 48 and the IF mixer 22 for analog correction of the output signal 46.
With an analog approach such as the conventional receiver of FIG. 1, the offsets are corrected quickly in wide bandwidth mode but the analog correction circuitry must be very precise itself. If the correction system is driven into a non-linear state because the offsets exceed the correction range or because there is excessive base band gain, the correction will be slew rate limited and may not meet the required correction cycle time of the loop. Further, loop analysis shows that such a C.T. analog DC offset loop creates a high-pass response in the forward gain path, wherein the high-pass corner is in the tens to hundreds of Hertz range. It has the tendency to track the incoming signal (not desired) if the bandwidth of the correction loop is made too large, for example greater than 30 Hertz (Hz) in frequency modulation (FM) voice applications. Yet if it is eliminated there will be a corresponding loss of signal dynamic range and clipping in the forward gain path. For direct conversion receivers this high pass corner creates a xe2x80x9cholexe2x80x9d in the desired signal bandwidth, which results in a finite Bit Error Rate (BER) floor. In VLIF receiver applications, the loop correction bandwidth can be made much larger as long as the lower half of the information bandwidth is greater than 0 Hertz, for example, 10 Kilohertz (kHz)-190 kHz in typical VLIF Global System for Mobile Communications (GSM) compatible integrated circuits. The variation in the analog components of the DC offset correction loop, however, create distortions which leak into the forward gain path also resulting in degraded radio performance. These problems in the analog approach have led engineers to consider digital implementations.
What is needed is an area-efficient,.high-gain, high-speed DC offset correction loop for use with both several cellular multiple access schemes (M.A.s) such as GSM and EDGE (Enhanced Data for GSM Evolution), Advanced Mobile Phone Service (AMPS), Narrow-band AMPS (NAMPS), North American Digital Cellular (NADC) or IS-136, and Code Division Multiple Access (CDMA), as well as with multiple receiver architectures such as direct conversion (DCR) and very low IF (VLIF).